The present disclosure generally relates to complementary metal-oxide semiconductor (CMOS) image sensors.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
FIG. 1 is a block diagram of an image sensor 100. Image sensor 100 includes an active pixel sensor (APS) pixel 102, a correlated double sampling (CDS) circuit 104 coupled to the APS pixel, and an analog-to-digital converter (ADC) circuit 106 coupled to the CDS circuit.
APS pixel 102 includes a pinned photodetector 108. Photodetector 108 includes a P-type body 110, an N-type implant 112, and a shallow pinning P-type implant 114 that separates the N-type implant from the surface. A transfer gate 116 controls the charge transfer from photodetector 108 to a floating diffusion (FD) node 118. A reset transistor 120 is coupled to FD node 118 to reset photodetector 108 before and after charge is integrated. A source follower (SF) transistor 122 is coupled to FD node 118 to convert charge to output voltage.
CDS circuit 104 includes a sample and hold reset (SHR) transistor 124 coupled to the source of SF transistor 122 to transfer a reset signal to a SHR capacitor 126 for storage. A sample and hold signal (SHS) transistor 128 is coupled to the source of SF transistor 122 to transfer a charge signal to a SHS capacitor 130 for storage. An amplifier 132 has its negative and positive inputs coupled to SHR capacitor 126 and SHS capacitor 130, respectively. Amplifier 132 outputs a signal that is the difference between the charge signal and the reset signal to remove reset noise.
ADC circuit 106 includes a comparator 134 with a negative input coupled to a ramp generator 136 and a positive input coupled to the output of amplifier 132. The output of comparator 134 is coupled to a latch 138 so the latch stores the value of a counter 140 when the signal from ramp generator 136 becomes larger than the signal from amplifier 132.